1. Field of the Invention
The present invention relates to a method of controlling a three-phase, three-level inverter and, in particular, to a control method of suppressing the variation of a neutral-point electrical potential of a capacitor contained in the inverter.
2. Description of the Related Art
FIG. 2 is a circuit diagram showing the arrangement of a conventional three-phase, three-level inverter presented, for example, in "A Current Control Scheme of Neutral-Point-clamped Voltage Source Inverters for Vector Control Systems", Thesis No. 113, Electrical Society, Industrial Application Department National Conference in 1989. In FIG. 2, the inverter includes a DC voltage source 1, a reactor 2 connected to the positive terminal of the DC voltage source 1, and a capacitor 3, one terminal P thereof being connected to the reactor 2 and the other terminal N thereof being connected to the negative terminal of the DC voltage source 1. The capacitor 3 is made up of a pair of capacitors 3a and 3b of the same rating, and a neutral-point terminal O is lead out from the point at which these capacitors are connected.
The inverter has pairs of transistors 4a-4b, 4c-4d, 5a-5b, 5c-5d, 6a-6b, and 6c-6d, each transistor of each pair being connected in serial. The first transistor pair 4a-4b and the second transistor pair 4c-4d, the third transistor pair 5a-5b and the fourth transistor pair 5c-5d, and the fifth transistor pair 6a-6b and the sixth transistor pair 6c-6d are respectively connected in serial, and these serial circuits are connected in parallel to each other between both of the terminals P and N of the capacitor 3. To each of the transistors 4a-4d, 5a-5d, and 6a-6d, free-wheeling diodes 7a-7d, 8a-8d, and 9a-9d are respectively reversely connected in parallel.
The cathodes of the first, third, and fifth diodes 10a, 11a, and 12a are respectively connected to the intermediate points of the first, third, and fifth transistor pairs. Each anode of these diodes is connected to the neutral-point terminal O of the capacitor 3. The anodes of the second, fourth, and sixth diodes 10b, 11b, 12b are respectively connected to the intermediate points of the second, fourth, and sixth transistor pairs. Each cathode of these diodes is connected to the neutral-point terminal O of the capacitor 3. Further, a U-phase output terminal T.sub.u is lead out from the connection point of the first transistor pair and the second transistor pair. A V-phase output terminal T.sub.v is lead out from the connection point of the third transistor pair and the fourth transistor pair. A W-phase output terminal T.sub.w is lead out from the connection point of the fifth transistor pair and the sixth transistor pair.
Next, the operation of the conventional inverter will be explained. First, the U phase will be taken as an example. The switching state of each of the transistors 4a to 4d of the U phase, i.e., the relationship between the on/off mode and the electrical potential of the output terminal T.sub.u, is shown in Table 1.
TABLE 1 ______________________________________ Electrical Potential of Output Transistor Transistor Transistor Transistor Terminal T.sub.u 4a 4b 4c 4d ______________________________________ E ON ON OFF OFF O OFF ON ON OFF -E OFF OFF ON ON ______________________________________
The output voltage of the DC voltage source 1 is taken to be 2E.
As shown above, the electrical potential of the output terminal T.sub.u has three kinds of values corresponding to the terminals P, N, and 0 of the capacitor 3, the particular value depending upon the switching state of the transistor. This is the reason why the inverter is called a three-level inverter. The same can be said about the V and W phases as has been said above about the U phase.
Next, the on/off mode of each transistor is in turn switched in order to take out the three phase outputs. It is considered that this on/off mode has a total of 3.sup.3 =27 kinds of modes. However, some of the on/off modes of these transistors have the same instantaneous space voltage vector (hereinafter referred to simply as a voltage vector) which is determined by the above-mentioned three kinds of electrical potentials. For this reason, there are a total 19 kinds of voltage vectors which are separate from each other. Table 2 summarizes the above relationship and shows the relationships among on/off modes M1 to M27, voltage vectors V0 to V18, and the output potentials V.sub.u, V.sub.v, and V.sub.w of each of the output terminals T.sub.u, T.sub.v, and T.sub.w.
It is necessary that the neutral-point terminal O of the capacitor 3 be primarily at a zero potential. In practice, however, it varies due to a load current I.sub.u, etc. supplied to the load from the output terminal T.sub.u, and so on. A technique for controlling the selection of the on/off mode in order to suppress the amount of this variation has been previously performed.
TABLE 2 ______________________________________ Output Potential On/off Mode Voltage Vector V u V v V w ______________________________________ M1 V0 E E E M2 O O O M3 -E -E -E M4 V1 E O O M5 O -E -E M6 V2 E -E -E M7 V3 E O -E M8 V4 O O -E M9 E E O M10 V5 E E -E M11 V6 O E -E M12 V7 O E O M13 -E O -E M14 V8 -E E -E M15 V9 -E E O M16 V10 -E O O M17 O E E M18 V11 -E E E M19 V12 -E O E M20 V13 O O E M21 -E -E O M22 V14 -E -E E M23 V15 O -E E M24 V16 O -E O M25 E O E M26 V17 E -E E M27 V18 E -E O ______________________________________
That is, as can be understood from Table 2, when a voltage vector V1 is output, M4 and M5, for example, can be selected as an on/off mode. Since the connection relationship among the neutral-point terminal O and the output terminal T.sub.u, and so on differ depending upon the on/off state of each transistor in both of the modes, the influence exerted on the electrical potential of the middle point terminal O by the load current I.sub.u, and so on will differ in both of the modes. Hence, the mode in which the electrical potential variation amount of the neutral-point terminal O is smaller is selected.
In the conventional three-phase, three-level inverter, the selection of the above-mentioned on/off mode performed in order to suppress the electrical potential variation amount of the neutral-point terminal O has been determined from a load current vector. That is, a load current vector is computed from the load currents I.sub.u, I.sub.v, and I.sub.w of each phase, and an on/off mode to be selected has been determined from the area of this load current vector.
Accordingly, as a computation process by which a load current vector is determined is required, the apparatus of the conventional invention becomes more complex and expensive.